The present invention is related to connecting IO from a semiconductor die to a package. More particularly, the present invention is related to systems and methods for connecting one of multiple interface types implemented on a semiconductor die to appropriate pins on different packages encapsulating a substantially similar semiconductor die.
A typical semiconductor design provides a number of IO buffers that are carefully placed around the periphery of a semiconductor die to be in proximity to package pins to which the IO buffers will be bonded. FIG. 1a shows an example of such a layout approach where a semiconductor die includes a number of IO buffers 110 surrounding the periphery of a semiconductor die 100, with each IO buffer 110 located in proximity to respective package pins 120. Each of IO buffers 110 include a single bond pad indicated by the cross-hatched area on the respective IO buffers 110. Some of IO buffers 110 are electrically coupled to package pins 120 by bonding wires 130. Other of the IO pads 110 are bonded to a ground plane 150 indicated by the lined area surrounding semiconductor die 100, or to a power plane 160 indicated by the stippled area surrounding semiconductor die 100. The different IO buffers are coupled to electrical circuitry on semiconductor die 100 that implement different interface types. In particular, IO buffer 110b and IO buffer 110c are electrically coupled to a circuit implementing an interface A. IO buffer 110d and IO buffer 110e are electrically coupled to a circuit implementing an interface B. IO buffer 110h, IO buffer 110i, IO buffer 110j, IO buffer 110k and IO buffer 110l are electrically coupled to a circuit implementing an interface C. IO buffer 110o, IO buffer 110p, IO buffer 110q, IO buffer 110r and IO buffer 110u are electrically coupled to a circuit implementing an interface D. IO buffer 110v and IO buffer 110w are electrically coupled to a circuit implementing an interface E; and IO buffer 110x and IO buffer 110y are electrically coupled to a circuit implementing an interface F.
Turning to FIG. 1b, one conventional circuit 199 for connecting an IO buffer to associated interface circuitry is depicted. Circuit 199 may be implemented for each of IO buffers 110 shown in FIG. 1a. Circuit 199 includes a semiconductor substrate 177 with a number of metal layers 162, 184, 188, 192, 196 disposed thereon. Each of metal layers 162, 184, 188, 192, 196 is separated from adjacent metal layers and semiconductor substrate 177 by insulating layers 164, 182, 186, 190, 194, 198. In addition, IO buffer 110 includes a bond pad 112. Bond pad 112 includes two bond pad layers 170, 171 interconnected by a number of vias 172. Bond pad 112 is further connected to underlying circuitry by way of a via 175. As shown, via 175 electrically couples bond pad 112 to a wire on metal layer 184, but could connect bond pad 112 to lower metal layers where such was desired.
In an ideal situation, bond wires 130 are as short as possible and extend directly to an adjacent package pin without crossing another bond wire or requiring any substantial directional changes. To accommodate this ideal situation, semiconductor die 100 of FIG. 1a may be designed such that IO buffers are located at the ideal locations such that they are aligned with respective package pins. Thus, a semiconductor die is often designed with some consideration of the final interfaces that will be supported and into which package the semiconductor die will be encapsulated. For most designs, such an approach is possible, however, it can be costly. In particular, while all interfaces are offered, the device may result in higher than necessary part costs and at times an uncompetitive price point for a given part. In addition, such an approach may result in inordinately high pin count packages that are not compatible with particular end designs or form factors.
Other approaches to reduce interfaces offered and thereby reduce pin count include implementing various versions of the semiconductor design that each contemplate a particular IO set and package. Such an approach, however, is costly as it requires the maintenance of different designs, the production of different semiconductor die, and in some cases a reduction of overall yield. Again, the aforementioned limitations may combine to render a device uncompetitive.
Another option is to implement a custom package design, or force a given semiconductor design into selected package that is not optimized for the semiconductor die. Neither option is ideal as a custom package design may introduce yield problems, and in any event may be costly. Turning to FIG. 1c, an example of forcing a particular die into a selected package is depicted. Semiconductor die 100 may be packaged in a package including fewer package pins compared with that shown in FIG. 1a. In such a case, the reduced number of package pins may reduce the number of interfaces that are implemented. Thus, as shown, only interface B, interface D, interface E and interface F are provided at the package pins. In using a different package, it may be necessary to use long bond wires 130 to extend from IO buffers associated with the desired interface circuitry and the selected package pins. While such an approach may be possible in some circumstances, it may not be ideal as the length of the bond wires is increased. Further, in some cases, such an approach may not be possible due to the length of bond wires and/or cross over between the bond wires with the potential of electrical shorts associated therewith.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for providing flexibility in packaging a semiconductor die and/or implementing the semiconductor die.